[[abstract]]We present cost and benefit models and analyze the economics effects of built-in self-test (BIST) for logic and memory cores. In our cost and benefit models for BIST, we take into consideration the design verification time and test development time associated with testability. Experimental results for logic BIST and memory BIST examples show that a threshold volume exists when BIST is profitable for the logic core under consideration—it is not recommended for a higher volume. However, BIST is a good choice for memory cores in general.[[fileno]]2030108030084[[department]]電機工程學
[[abstract]]Memory testing is becoming the dominant factor in testing a system-on-chip (SOC), with t...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005.The dissertation investigates...
With the advent of deep-submicron VLSI technology, core-based system-on-chip (SOC) design is attract...
[[abstract]]© 2007 Institute of Electrical and Electronics Engineers - The demand for built-in self-...
[I]. Note that manufacturing test is applied to every device multiple times, at different voltage le...
Abstract—Memory is increasingly important because of the high density of current memory chips. W...
Abstract—Built-in self-test (BIST) is a well-known design technique in which part of a circuit is us...
The design and architecture of a reconfigurable memory BIST unit is presented. The proposed memory B...
The integrated circuit scaling has been following the Moore’s Law since 1965 [59, 60, 61]. Within th...
Abstract—Although integrated circuits (IC) shrink in size as the fabrication technology progresses, ...
A Built-in self-test technique constitute a class of algorithms that provide the capability of perfo...
Abstract—As there are increasing functionalities in modern system-on-chip (SOC) design, the amount o...
The burgeoning amount and complexity of memories in modern SoC have brought forth new challenges in ...
To evaluate the effectiveness of built-in self-test (BIST) for logic circuits, the test design autom...
With higher computerization in the automobile stream, the built-in self-test is essential for high q...
[[abstract]]Memory testing is becoming the dominant factor in testing a system-on-chip (SOC), with t...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005.The dissertation investigates...
With the advent of deep-submicron VLSI technology, core-based system-on-chip (SOC) design is attract...
[[abstract]]© 2007 Institute of Electrical and Electronics Engineers - The demand for built-in self-...
[I]. Note that manufacturing test is applied to every device multiple times, at different voltage le...
Abstract—Memory is increasingly important because of the high density of current memory chips. W...
Abstract—Built-in self-test (BIST) is a well-known design technique in which part of a circuit is us...
The design and architecture of a reconfigurable memory BIST unit is presented. The proposed memory B...
The integrated circuit scaling has been following the Moore’s Law since 1965 [59, 60, 61]. Within th...
Abstract—Although integrated circuits (IC) shrink in size as the fabrication technology progresses, ...
A Built-in self-test technique constitute a class of algorithms that provide the capability of perfo...
Abstract—As there are increasing functionalities in modern system-on-chip (SOC) design, the amount o...
The burgeoning amount and complexity of memories in modern SoC have brought forth new challenges in ...
To evaluate the effectiveness of built-in self-test (BIST) for logic circuits, the test design autom...
With higher computerization in the automobile stream, the built-in self-test is essential for high q...
[[abstract]]Memory testing is becoming the dominant factor in testing a system-on-chip (SOC), with t...
118 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005.The dissertation investigates...
With the advent of deep-submicron VLSI technology, core-based system-on-chip (SOC) design is attract...