[[abstract]]For the first time, we implemented a reconfigurable load-balanced TDM switch for high speed networking applications. An N×N TDM switch could be constructed recursively from the proposed switch modules to achieve switching capacity of hundred gigabits per second or higher. Two architectures were implemented. One was an 8×8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet applications. The other was a dual-mode 8×8 or 64×64 TDM switch with parallel ports. A novel testing circuit was also implemented to easily verify switching results. Our results showed a 20 Gbps switching capacity for the 8×8 TDM switch with parallel input and output ports and a 640 Gbps capacity for the 64×64 switch. All implement...
The master’s thesis is focused on desing high-speed ethernet switch based on circuit FPGA. The switc...
The physical layer, data plane design of an all-optical network switch capable of scaling to 1024 po...
The design of a high speed, broadband packet switch with two priority levels for application in inte...
[[abstract]]For the first time, we implemented a reconfigurable load-balanced TDM switch for high sp...
[[abstract]]© 2007 Institute of Electrical and Electronics Engineers - For the first time, we implem...
[[abstract]]© 2007 Institute of Electrical and Electronics Engineers - For the first time, a scalabl...
Abstract For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES...
High-speed networks used to interconnect computers advance at an extraordinary pace, driven by the e...
Abstract — The load-balanced switch architecture is a promis-ing way to scale router capacity. We ex...
Abstract — The load-balanced switch architecture is a promising way to scale router capacity. We exp...
Abstract — The load-balanced switch architecture is a promising way to scale router capacity. We exp...
Current technology trends make it possible to build communication networks that can support high pe...
It is the objective of this thesis to investigate a number of issues associated with building a sc...
We have developed an architecture for an IRAM-based ATM switch that is implemented with merged DRAM ...
[[abstract]]© 1989 Institute of Electrical and Electronics Engineers-A novel VLSI message switch des...
The master’s thesis is focused on desing high-speed ethernet switch based on circuit FPGA. The switc...
The physical layer, data plane design of an all-optical network switch capable of scaling to 1024 po...
The design of a high speed, broadband packet switch with two priority levels for application in inte...
[[abstract]]For the first time, we implemented a reconfigurable load-balanced TDM switch for high sp...
[[abstract]]© 2007 Institute of Electrical and Electronics Engineers - For the first time, we implem...
[[abstract]]© 2007 Institute of Electrical and Electronics Engineers - For the first time, a scalabl...
Abstract For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES...
High-speed networks used to interconnect computers advance at an extraordinary pace, driven by the e...
Abstract — The load-balanced switch architecture is a promis-ing way to scale router capacity. We ex...
Abstract — The load-balanced switch architecture is a promising way to scale router capacity. We exp...
Abstract — The load-balanced switch architecture is a promising way to scale router capacity. We exp...
Current technology trends make it possible to build communication networks that can support high pe...
It is the objective of this thesis to investigate a number of issues associated with building a sc...
We have developed an architecture for an IRAM-based ATM switch that is implemented with merged DRAM ...
[[abstract]]© 1989 Institute of Electrical and Electronics Engineers-A novel VLSI message switch des...
The master’s thesis is focused on desing high-speed ethernet switch based on circuit FPGA. The switc...
The physical layer, data plane design of an all-optical network switch capable of scaling to 1024 po...
The design of a high speed, broadband packet switch with two priority levels for application in inte...