Add to ORKG[[abstract]]We demonstrate a 2D parallel pipelined system using smart pixel array cellular logic (SPARCL) processors and show how it outperforms SIMD systems. This paper examines two architectures based on an n stage smart pixel array cellular logic (nSPARCL) processor system that relieves the I/O bottleneck using free-space digital optics. The SPARCL chip is a SIMD processor array in which PEs are implemented by smart pixels[[fileno]]2030122030014[[department]]電機工程學
As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing arr...
In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies...
A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presente...
[[abstract]]We describe the chip design and system implementation of an optoelectronic parallel pipe...
[[abstract]]© 1996 Institute of Electrical and Electronics Engineers - We are developing a free-spac...
[[abstract]]We present the architecture and optical design for a smart pixel optoelectronic system t...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
Abstract—This paper describes an architecture and implemen-tation of a digital vision chip that feat...
Many networked embedded systems combine sensing using cameras with processing to achieve certain com...
This paper presents a new processing cell circuit, suitable for use in massively parallel fine-grain...
ABSTRACT: This paper discusses issues related to the efficiency of silicon implementations of cellul...
Vision chips are microelectronic devices which combine image sensing and processing on a single sili...
A prototype cellular logic array processor (CLAP-4), which has been indigenously constructed using T...
Sophisticated computational imaging algorithms require both high performance and good energy-efficie...
Abstract — In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pi...
As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing arr...
In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies...
A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presente...
[[abstract]]We describe the chip design and system implementation of an optoelectronic parallel pipe...
[[abstract]]© 1996 Institute of Electrical and Electronics Engineers - We are developing a free-spac...
[[abstract]]We present the architecture and optical design for a smart pixel optoelectronic system t...
International audienceA high-speed analog VLSI image acquisition and low-level image processing syst...
Abstract—This paper describes an architecture and implemen-tation of a digital vision chip that feat...
Many networked embedded systems combine sensing using cameras with processing to achieve certain com...
This paper presents a new processing cell circuit, suitable for use in massively parallel fine-grain...
ABSTRACT: This paper discusses issues related to the efficiency of silicon implementations of cellul...
Vision chips are microelectronic devices which combine image sensing and processing on a single sili...
A prototype cellular logic array processor (CLAP-4), which has been indigenously constructed using T...
Sophisticated computational imaging algorithms require both high performance and good energy-efficie...
Abstract — In this paper we present a vision processor, which incorporates a 160×80 SIMD array of pi...
As inexpensive imaging chips and wireless telecommunications are incorporated into an increasing arr...
In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies...
A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presente...