[[abstract]]To successfully route a design, one essential requirement is to allocate sufficient routing resources. In this paper, we show that allocating routing resources based on horizontal and vertical (H/V) cut-demands can greatly improve routability especially for designs with thin areas. We then derive methods to predict the maximum H/V cut-demands and propose two cut-demand based approaches, one is to allocate routing resources considering the maximum H/V cut-demands and the other is to consolidate fragmented metal-1 routing resources for effective resource utilization. Experimental results demonstrate that the resource allocation method can precisely determine design areas and the resource consolidation method can significantly impr...
Abstract — This article describes an algorithm for curvilinear detailed routing. We significantly im...
Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critic...
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as pos...
One of the vital phases in the design flow of electronic artifacts is the phase called physical desi...
Increasing challenges arise with each new semiconductor technology node, especially in advanced node...
For the last several technology generations, VLSI designs in new technology nodes have had to confro...
Abstract—For the last several technology generations, VLSI designs in new technology nodes have had ...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
This dissertation addresses for the first time the integrated problem of designing the manufacturing...
For the congestion issue, we found that the existing congestion models will very often over-estimate...
The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layer...
This project included two parts. First, a reconfigurable cell was designed as the DataPath Unit (DPU...
Abstract — This article describes an algorithm for curvilinear detailed routing. We significantly im...
Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critic...
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as pos...
One of the vital phases in the design flow of electronic artifacts is the phase called physical desi...
Increasing challenges arise with each new semiconductor technology node, especially in advanced node...
For the last several technology generations, VLSI designs in new technology nodes have had to confro...
Abstract—For the last several technology generations, VLSI designs in new technology nodes have had ...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
This dissertation addresses for the first time the integrated problem of designing the manufacturing...
For the congestion issue, we found that the existing congestion models will very often over-estimate...
The progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layer...
This project included two parts. First, a reconfigurable cell was designed as the DataPath Unit (DPU...
Abstract — This article describes an algorithm for curvilinear detailed routing. We significantly im...
Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critic...
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and...