Clock tree regeneration

[[abstract]]We present in this paper a clock tree regeneration algorithm for improving both the wirability and performance of VLSI chip designs. After circuit placement, we modify the clock trees originally specified by logic designs utilizing the geometrical information derived from the placement. First, a bipartite bottleneck matching approach is applied to minimize the longest driver to clock pin length. Then a linear assignment approach is used to optimize the total driverpin length. The experimental results are extremely encouraging.[[fileno]]2030222030002[[department]]資訊工程學