Add to ORKG[[abstract]]To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among modules, whereas the module-level CTO reduces clock skew within a single module. Our experimental results show that the power-mode-aware CTO can achieve significant improvement in the worst-case condition with only a minor penalty in area.[[fileno]]2030219030051[[department]]資訊工程學
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
As power consumption of the clock tree in modern VLSI de-signs tends to dominate, measures must be t...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
Among the most challenging tasks of advanced-node IC design is power reduction. In the advanced tech...
[[abstract]]Clock skew optimization is a complicated problem in modern VLSI technologies because cir...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
Our work concentrates on high-level optimization of the power of clock network, which is a relativel...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...
In a synchronous clock distribution network with negligible skews, digital circuits switch simultane...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
The buffered clock tree structure is commonly used to distribute the clock signal to the memory elem...
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an es...
In synchronous circuit design, data is processed in an orderly fashion with the help of sequential e...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The fun...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
As power consumption of the clock tree in modern VLSI de-signs tends to dominate, measures must be t...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
Among the most challenging tasks of advanced-node IC design is power reduction. In the advanced tech...
[[abstract]]Clock skew optimization is a complicated problem in modern VLSI technologies because cir...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
Our work concentrates on high-level optimization of the power of clock network, which is a relativel...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...
In a synchronous clock distribution network with negligible skews, digital circuits switch simultane...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
The buffered clock tree structure is commonly used to distribute the clock signal to the memory elem...
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an es...
In synchronous circuit design, data is processed in an orderly fashion with the help of sequential e...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The fun...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
As power consumption of the clock tree in modern VLSI de-signs tends to dominate, measures must be t...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...