Datapath optimization using layout information: An empirical study

[[abstract]]Most datapath synthesis approaches use a simple area model to evaluate design area quality. However, using such a simplified model could mislead synthesis tasks into generating inferior designs. This paper presents an extensive experimental study to validate the correlation between the tradition area model, our proposed area model, and the actual layouts. The results show that traditional area quality measures are not good indicators for optimization in datapath synthesis. Moreover, this paper also shows that to provide accurate indications for design tradeoffs in high-level synthesis, the fidelity of the estimates is more important than the accuracy.[[fileno]]2030214010008[[department]]資訊工程學