Concurrent-simulation-based remote IP evaluation over the Internet for system-on-a-chip design

[[abstract]]We propose an Internet-based concurrent-simulation scheme to ease intellectual property (IP) evaluation process between IP vendors and users. Complex system-on-a-chip (SOC) design requires more and more IP modules from third party vendors. What can be disclosed by the vendor without impairing its trade secret and what needs to be examined by the user to gain satisfactory level of confidence are contradictory of each other. Via PLI interface functions and Internet protocol, our proposed software enables HDL simulators (Verilog) residing in both the vendor and user's sites to concurrently simulate the IP and SOC together. Only stimulus and response defined in the IP's I/O are exchanged between the sites. Therefore, the vendor need not to create a functional model (or encrypted code) for the IP while the user is assured what he/she simulates is what he/she will purchase. Beside simulation speed degradation due to communication overhead, the. SOC design/debug process is exactly same as if the IP is in the user's hand. Our contribution will help all IP providers expose their IPs to all potential users without human intervention and IP right infringement concern[[fileno]]2030207030068[[department]]資訊工程學