A hardware accelerator for H.264/AVC motion compensation

[[abstract]]We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports all advanced features including variable-block-size motion estimation from multiple reference frames for both P and B slices, quarter-pixel accuracy, and weighted bi-directional prediction. We pay special attention to memory subsystem design for optimizing both memory usage and memory bandwidth. We have integrated the accelerator into an H.264/AVC main profile decoder in FPGA prototype. Compared with previous work, our accelerator is smaller and faster.[[fileno]]2030207030020[[department]]資訊工程學