Preserving HDL synthesis hierarchy for cell placement

[[abstract]]We propose an integrated HDL-synthesis and placement method for row-based layouts. Our approach bridges the gap between HDL synthesis and placement by fully utilizing design hierarchy. It first synthesizes an HDL design specification into a hierarchy of subcircuits. It then groups subcircuits to form strongly connected macro cells, followed by performing a macro-cell placement to determine the location of the macro cells on the layout plane. Finally, it maps the resulting macro-cell placement into a row-based placement and applies a simulated-annealing procedure to refine the row-based placement. Experiments on a number of large industry designs demonstrate that the proposed method achieves, on the average, 22% area reduction, 18% wire length reduction, and several times of speed up compared to that without the hierarchy information.[[fileno]]2030207030003[[department]]資訊工程學