System and method for extracting parasitic impedance from an integrated circuit layout

[[abstract]]A comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines of an integrated circuit. The method includes collecting values of electrical characteristic parameters to provide a technology profile for a particular fabrication process. An Interconnect Primitive Library builder provides a collection of interconnect `primitives` that any interconnect structure fabricated under the fabrication process can be broken down into, and combines it with the technology profile for simulations in a 3-dimensional field solver to extract parameterized coupling capacitances and other characteristic impedances for each interconnect primitive. An extraction tool traces a signal path of an integrated circuit and decomposes the interconnect structures on the signal path into interconnect primitives and maps them to the Interconnect Primitive Library. An RC network module provides an RC network based on the characterized parametric values in the mapped interconnect primitives. The RC network thus provided can be used to accurately estimate signal delays in a circuit simulator or delay calculator.[[fileno]]2030232060007[[department]]資工