Add to ORKG[[abstract]]A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.[[fileno]]2020309060044[[department]]材料科學工程學
[[abstract]]The capacitor, e.g. of a DRAM cell, is formed by depositing a first layer of hemispheric...
[[abstract]]A semiconductor fabrication method is provided for the fabrication of a dielectric struc...
[[abstract]]A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next...
[[abstract]]A structure of a capacitor includes two gates and a commonly used source/drain region on...
[[abstract]]A method for fabricating a capacitor of a DRAM includes a lower conductive layer of the ...
[[abstract]]A method for forming a dielectric-constant-enhanced capacitor is provided. A wafer in a ...
[[abstract]]A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion...
[[abstract]]A method of forming a DRAM includes forming a transfer FET on a substrate, the FET havin...
A method of manufacturing a capacitor on a wafer, and an IC comprising such a capacitor is disclosed...
[[abstract]]A method for manufacturing the lower electrode of a DRAM capacitor. The method includes ...
[[abstract]]A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming...
[[abstract]]A fabrication method for an integrated device having a capacitor in an interconnect syst...
A method of creating a capacitor in an integrated circuit. According to a basic version of the inven...
[[abstract]]A method for forming a DRAM capacitor whose titanium nitride electrode is fabricated in ...
[[abstract]]A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact ...
[[abstract]]The capacitor, e.g. of a DRAM cell, is formed by depositing a first layer of hemispheric...
[[abstract]]A semiconductor fabrication method is provided for the fabrication of a dielectric struc...
[[abstract]]A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next...
[[abstract]]A structure of a capacitor includes two gates and a commonly used source/drain region on...
[[abstract]]A method for fabricating a capacitor of a DRAM includes a lower conductive layer of the ...
[[abstract]]A method for forming a dielectric-constant-enhanced capacitor is provided. A wafer in a ...
[[abstract]]A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion...
[[abstract]]A method of forming a DRAM includes forming a transfer FET on a substrate, the FET havin...
A method of manufacturing a capacitor on a wafer, and an IC comprising such a capacitor is disclosed...
[[abstract]]A method for manufacturing the lower electrode of a DRAM capacitor. The method includes ...
[[abstract]]A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming...
[[abstract]]A fabrication method for an integrated device having a capacitor in an interconnect syst...
A method of creating a capacitor in an integrated circuit. According to a basic version of the inven...
[[abstract]]A method for forming a DRAM capacitor whose titanium nitride electrode is fabricated in ...
[[abstract]]A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact ...
[[abstract]]The capacitor, e.g. of a DRAM cell, is formed by depositing a first layer of hemispheric...
[[abstract]]A semiconductor fabrication method is provided for the fabrication of a dielectric struc...
[[abstract]]A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next...