Development and Implementation of the Circuit-Level Oxide Reliability Switch Matrix Technique for Evaluation of CMOS DC and AC Circuit Performance Characteristics

Circuit-level oxide degradation effects on inverter circuit operation and individual MOSFET behavior was investigated using 160 nm CMOS technology. The switch matrix technique (SMT), developed for this research, is instrumental for configuring the inverter or other simple circuits. Ultimately, SMT enables both characterization and stress tests to be performed at the transistor and circuit-levels. Following an applied ramped voltage stress (RVS) of various magnitudes, increased MOSFET gate oxide leakage currents of nearly eight orders of magnitude are observed. Gate oxide stress in the MOSFETs also results in significant changes to the intrinsic device characteristics. Comparison of the CMOS inverter performance in the DC versus AC domain shows that the AC voltage-time (V -t) domain results in significantly larger changes as a result of stress. Therefore, in this study, it is proposed that the V-t characteristics may be more influential when determining circuit reliability limitations. A preliminary circuit-level oxide degradation model was created using HSPICE to provide a possible physical explanation for observed degradation in the inverter DC characteristics. From a circuit reliability viewpoint, it may be possible for subsequent circuit stages to compensate for a few degraded devices, but in high-speed circuits, increased transition times and propagation delays may cause timing issues. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages and result in increased power consumption