Hardware Implementation of Finite State Machine Watermarking Technique

In today\u27s competitive and outsourced market a company\u27s Intellectual Property (IP) is always at very high risk. It has become quite easy to commercialize products by reverse engineering and reproducing someone else\u27s product. Hence protecting one\u27s designs has become high priority for most of the IP owners. Recently there has been a lot of research in the field of digital watermarking for copyright protection of IP blocks. In this research, we implement a new approach for watermarking IP design. This technique embeds a robust watermark in the IP design\u27s Finite State Machine (FSM) by making use of coinciding as well as unused transitions in the state transition graph. This is a first of its kind public key IP watermarking scheme implementation at the FSM level used as copyright protection technique. The implementation of algorithms is done in VHDL where a signature is embedded into the FSM resulting in a robust watermarked design. For experimental comparison and analysis, designs from the IWLS93 benchmark circuits have been used. FSM designs were watermarked using a VHDL entity, utilizing the Xilinx ModelSim tool suite. To ensure that the resulting watermarked FSM shows the same behavior as that of the original FSM, a test bench was developed and simulated on all of the benchmark circuits before and after the watermark insertion. The watermarked FSM was then converted to a sequential VHDL module which could be synthesized using the Xilinx ISE Project Navigator tool. Data extracted from this simulation concluded that since this scheme makes use of used as well as unused transitions, the level of robustness increases and securely implements an IP design