A novel message switch for highly parallel systems

[[abstract]]© 1989 Institute of Electrical and Electronics Engineers-A novel VLSI message switch design for application in highly parallel architectures is presented. The prominent features of this design are message combining, a shared central queue structure with a dynamic boundary and nonpreemptive priority, and a look-ahead protocol between switch nodes in adjacent stages. These features alleviate memory contention and increase the effective network bandwidth[[fileno]]2030118030003[[department]]電機工程學