VLSI systolic multiplier and adder for digital signal processing

[[abstract]]© 1991 Elsevier-The authors describe high throughput arithmetic units that can be used to implement efficient processing elements of a 2-D FIR filter. The include a bit-level systolic multiplier which multiplies input data by a weighting coefficient, a bit-level systolic adder which computes intermediate summation results and a multiple-number systolic adder which performs the addition of M parallel available numbers. These units have the advantages of systolic arrays. Since the most complex cell in the design is a single-bit full adder, these structures can be easily implemented on MOS technology. Besides, the delay time of the slowest cell is quite small;therefore throughput rate is much higher than other solutions[[department]]電機工程學