Reduced processing element architecture for parallel local image processing

[[abstract]]© 1987 中國工程師學會-For large-sized local image processing, this architecture will save much space as it is suitable for design into a VLSI chip. For example, the traditional parallel architecture will use 9 processing elements for a 3×3 convolution, while the Reduced Processing Element Architecture only requires 2 to achieve the real-time performance[[department]]電機工程學