EFFICIENT BIT-LEVEL SYSTOLIC ARRAY IMPLEMENTATION OF FIR AND IIR DIGITAL FILTERS

[[abstract]]© 1988 Institute of Electrical and Electronics Engineers - Bit-level systolic architectures based on an inner-product computation scheme for finite impulse are presented that are based on a new inner-product computation scheme for finite-impulse response (FIR) and infinite-impulse-response (IIR) digital filters. The FIR filter structure is optimized in the sense that for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required.[[department]]電機工程學