A new systolic architecture for fast exponentiation in GF(2m)

[[abstract]]© 1995 National Taiwan University - This paper presents a new parallel-in parallel-out systolic array for computing exponentiations in GF(2m). The architecture is constructed by using m-1 basic circuits for the operation AB2 in GF(2m). It possesses the desirable features of regularity and modularity for VLSI implementation and is capable of producing results at a rate of one per clock cycle. As compared to existing systolic designs with the same throughput performance for exponentiation in GF(2m), the proposed one has smaller latency and smaller area requirement. In addition, it involves unidirectional data flow, and is easy to incorporate fault tolerant design[[department]]電機工程學