A new systolic architecture for fast DCT computation

[[abstract]]© 1996 Institute of Electrical and Electronics Engineers - This paper presents a fast algorithm along with its systolic array implementation for computing the 1-D N-point discrete cosine transform (DCT), where N is a power of two. The architecture requires log2N multipliers and can evaluate one complete N-point DCT every N clock cycles. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing systolic DCT architectures reaching the same throughput performance, the proposed one involves much less hardware complexity.[[department]]電機工程學