[[abstract]]© 1992 Elsevier - The paper presents a new word-level systolic array with no broadcasting for implementation of 2-D FIR digital filters. The architecture possesses the desirable features of regularity, modularity, and concurrency for VLSI implementation. As compared to existing related systolic systems with broadcasting, it achieves improved throughput performance with a little increase in the latency and the number of latches. Also, the proposed array has an important feature that the filter coefficients can easily be updated without interrupting the system operations. This makes it attractive for use in applications such as adaptive image processing and image template matching[[department]]電機工程學
[[abstract]]© 1994 Institute of Electrical and Electronics Engineers - The delayed least-mean-square...
In this paper, we present an efficient poly-phase decomposition scheme for implementation of 2-D non...
A technique for mapping systolic FIR filter banks onto fixed-size processor arrays is presented. It ...
[[abstract]]© 1991 Elsevier-The authors describe high throughput arithmetic units that can be used t...
[[abstract]]Bit-level systolic architectures based on an inner-product computation scheme for finite...
[[abstract]]© 1988 Institute of Electrical and Electronics Engineers - Bit-level systolic architectu...
A novel VLSI (Very Large Scale Integration) architecture for real time IIR (Infinite Impulse Respons...
[[abstract]]Flexible VLSI architectures for high-speed 2-D finite-impulse-response (FIR) and infinit...
In this thesis, we propose efficient systolic array architectures for the 1-D and the 2-D discrete F...
This paper describes the VLSI design of a high-speed single-chip FIR filter for data with a limited ...
The tremendous growth of computer and Internet technology wants a data to be process with a high spe...
Abstract – In this paper we present 1D and 2D systolic Distributed Arithmetic (DA) based structures ...
[[abstract]]© 1991 Institute of Electrical and Electronics Engineers - In this paper, a bit-level sy...
This paper presents ongoing work on the design of a two-dimensional (2D) systolic array for image pr...
[[abstract]]Flexible VLSI architectures for realizing high-speed 2-D FIR (finite impulse response) a...
[[abstract]]© 1994 Institute of Electrical and Electronics Engineers - The delayed least-mean-square...
In this paper, we present an efficient poly-phase decomposition scheme for implementation of 2-D non...
A technique for mapping systolic FIR filter banks onto fixed-size processor arrays is presented. It ...
[[abstract]]© 1991 Elsevier-The authors describe high throughput arithmetic units that can be used t...
[[abstract]]Bit-level systolic architectures based on an inner-product computation scheme for finite...
[[abstract]]© 1988 Institute of Electrical and Electronics Engineers - Bit-level systolic architectu...
A novel VLSI (Very Large Scale Integration) architecture for real time IIR (Infinite Impulse Respons...
[[abstract]]Flexible VLSI architectures for high-speed 2-D finite-impulse-response (FIR) and infinit...
In this thesis, we propose efficient systolic array architectures for the 1-D and the 2-D discrete F...
This paper describes the VLSI design of a high-speed single-chip FIR filter for data with a limited ...
The tremendous growth of computer and Internet technology wants a data to be process with a high spe...
Abstract – In this paper we present 1D and 2D systolic Distributed Arithmetic (DA) based structures ...
[[abstract]]© 1991 Institute of Electrical and Electronics Engineers - In this paper, a bit-level sy...
This paper presents ongoing work on the design of a two-dimensional (2D) systolic array for image pr...
[[abstract]]Flexible VLSI architectures for realizing high-speed 2-D FIR (finite impulse response) a...
[[abstract]]© 1994 Institute of Electrical and Electronics Engineers - The delayed least-mean-square...
In this paper, we present an efficient poly-phase decomposition scheme for implementation of 2-D non...
A technique for mapping systolic FIR filter banks onto fixed-size processor arrays is presented. It ...