A Reconfigurable Multicomputer System: Implementation And Performance

Architecture of the computer has always been dictated by the attribute considered the most important during its design. The classical von Neumann computer system was the consequence of a quest for reliability; the modern multiple-processor architectures have resulted from a search for performance. While the modern system\u27s existence is based on its relative reliability, its efficiency depends upon the match between the problem\u27s inherent structure and the system\u27s architecture. The architecture of a typical multiple-processor machine is fixed: essentially it either supports simultaneous, or sequential task solutions with efficiency. Since most computer-tractable problems are neither purely parallel nor serial, the machine whose architecture can be configured to match the problem would offer higher performance in a broader range of applications than its fixed-architecture counterpart. Clearly, a real-time reconfigurable machine would then provide an optimal problem-architecture match.;This thesis introduces a research-oriented, high performance, Reconfigurable Multicomputer System (RMCS), which combines versatility, connectivity, and incremental expandability. The prototype system that has been designed, implemented, and characterized, comprises an elemental cell of four autonomous processors (slaves), an Interprocessor Communication Network (ICN) that supports the reconfigurability, and a network controller module. A supervisory processing unit (the master), provides the slaves with instructions and data for a task, and synchronizes their activity. The ICN features a number of Programmable Signal Routers (PSR) which were designed and fabricated at the silicon chip level to implement the unique architecture. The ICN provides unidirectional and exclusive data communications among the processors. The system is expandable by replicating the elemental cell; a single master is employed for systems of any size. The chosen architecture warrants eventual VLSI implementation of large multi-celled systems.;A prototype of the reconfigurable multicomputer has been built and the characteristics critical to its performance and future optimization determined. The PSR electrical behaviour, interprocessor data communications, synchronization overhead, and computational performance have been tested. The performance tests, chosen to encompass typical applications, include matrix operations, Fast Fourier Transform computations, frequency domain filtering, and alternating series calculations. The tests utilize various computational and control strategies, which exploit the system\u27s reconfigurability and demonstrate its efficacy. The performance advantage of the RMCS architecture is compared to that of a congruent uniprocessor, executing the same task, yielding thus a speed-up factor as the main measure of the performance increase. The experiments evince the effect of the ICN and control strategies on overall performance. Results may be scaled for systems of different size and sophistication.;The RMCS performance speed-up is task, problem-size, and control-strategy sensitive. Nearly ideal speed-up factors were obtained for parallel matrix multiplication, as well as for alternating series computations using parallel/pipelined mode. Parallel FFT tests yielded speed-up factors from 2.7 to 4.2 for 256-point complex series. The frequency domain filtering experiments took greater advantage of the system\u27s reconfigurability, resulting in improved performance. The experiments provided sufficient data to develop an accurate performance model.;The study established the viability of the reconfigurable multicomputer architecture and demonstrated its advantages in scientifically-oriented computations