Blockage-Aware Routing Tree Construction with Concurrent Buffer and Flip-Flop Insertion

[[abstract]]©2007 SASIMI-For high-frequency designs, concurrent buffer and flip-flop insertion becomes inevitable for interconnect delay optimization. To the best of our knowledge, all existing works perform concurrent buffer and flip-flop insertion on a given routing tree. The given routing tree, however, may greatly limit the effectiveness of concurrent buffer and flip-flop insertion. In this paper, we present a method which simultaneously constructs a routing tree and performs concurrent buffer and flip-flop insertion subject to latency constraints. We also propose four speed-up techniques to further reduce the computation time. The experimental results show that our method has 90% success rate in generating a feasible solution while a sequential method, which separates the tree construction and the concurrent buffer and flip-flop insertion into 2 steps, has only 57% success rate. For the test cases in which both our method and the sequential method can generate feasible solutions, our method has up to 96% chance to produce better solutions.[[department]]資訊工程學