Software and hardware co-design for MP3 decoder

[[abstract]]The RISC architecture is a load-store architecture that its data processing operations execute only on registers. The signal processing application requires many data computations. It takes many resources to execute data movements and operations. Therefore, the performance of the signal processing application is limited on traditional RISC architecture. In this paper, ARM processor and MP3 decoder are selected as the RISC architecture platform and signal processing application, respectively. Moreover, because the signal processing application can not execute efficiently on traditional RISC architecture, both software optimization and architecture enhancement will be used to improve the performance of the system. The experimental results have shown great performance improvements in the system (17 refs.)[[fileno]]2030240030025[[department]]資訊工程學