An HMAC processor with integrated SHA-1 and MD5 algorithms

[[abstract]]A built-in self-test (BIST) compiler for embedded memories, called BRAINS (Bist for RAm IN Seconds), is proposed. According to the memory specifications and test requirements entered by the user, BRAINS generates the synthesizable BIST code in Verilog as well as the corresponding BIST activation sequence and test-bench. The synthesis scripts for a commercial synthesis tool also are generated automatically. The architecture for the BIST circuits generated by BRAINS is an improved version of our previous design. The new design provides at-speed testing, diagnosis support, and programmable March test algorithms. The BIST compiler framework facilitates the generation of BIST circuits for various SRAM and DRAM architectures and configurations-BRAINS supports commonly used memory cores such as SRAM, EDO DRAM, SDRAM, etc. It is easy to use BRAINS for customized embedded memories. We have designed the system so that future extension to other types of memory can be done under the same framework.[[fileno]]2030243030005[[department]]資訊工程學