A highly efficient AES cipher chip

[[abstract]]We present an efficient hardware implementation of the AES (advanced encryption standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of the S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0.25 /spl mu/m CMOS technology, the throughput rate is 2.977 Gbps for 128 bit keys, 2.510 Gbps for 192 bit keys, and 2.169 Gbps for 256 bit keys, with a 250 MHz clock. Testability of the design is also considered. The area of the core circuit is about 1,279/spl times/1,271 /spl mu/m/sup 2/.[[fileno]]2030243030031[[department]]資訊工程學