Test Scheduling of BISTed Memory Cores for SOC

[[abstract]]The test scheduling of memory cores can significantly affectthe test time and power of system chips. We propose atest scheduling algorithm for BISTed memory cores to minimizethe overall testing time under the test power constraint.The proposed algorithm combines several approaches for anear-optimal result, based on the properties of BISTed memorycores. By proper partitioning, an analytic exhaustivesearch finds optimal results for large memory cores, while aheuristic ordering with simulated annealing further handlesa large amount of smaller memory cores. On the average,the results are within 1% difference of the optimal solutionfor the cases of 200 memory cores.[[fileno]]2030243030029[[department]]資訊工程學