[[abstract]]Testing for performance problems of FPGAs has become an important task for ever-increasingly advanced technology. To develop effective testing methodologies, a tool to independently evaluate the quality of test configurations is therefore much needed. In this paper, we present a method to calculate coverages of randomly distributed multiple delay defects in FPGAs. The evaluation algorithm can also identify target paths which are not covered in the current configurations, but can contribute to the quality of the tests. It is shown that the reported metrics can be used to quantify the coverage of delay defects and also further improve high-quality test configurations.[[fileno]]2030243030009[[department]]資訊工程學
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic archite...
[[abstract]]© 2005 Institute of Electrical and Electronics Engineers -Testing for performance proble...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
Abstract detection of delay faults is generally reported by showingfault coverage values for commonl...
This Master s thesis documents a new test method for detection of small delay faults in FPGA routing...
[[abstract]]Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we e...
108 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.We use circuit delay bounding...
108 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.We use circuit delay bounding...
[[abstract]]This paper defines a new diagnosis problem for diagnosing delay defects based upon stati...
[[abstract]]The problem of diagnosing delay defects is defined using a statistical timing model. The...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic archite...
[[abstract]]© 2005 Institute of Electrical and Electronics Engineers -Testing for performance proble...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
Abstract detection of delay faults is generally reported by showingfault coverage values for commonl...
This Master s thesis documents a new test method for detection of small delay faults in FPGA routing...
[[abstract]]Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we e...
108 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.We use circuit delay bounding...
108 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.We use circuit delay bounding...
[[abstract]]This paper defines a new diagnosis problem for diagnosing delay defects based upon stati...
[[abstract]]The problem of diagnosing delay defects is defined using a statistical timing model. The...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic archite...