[[abstract]]A simple priority scheme called separate queues with complete buffer sharing (SQCS) is proposed for the ATM switches. In this scheme, buffers are shared for the two priority classes but two logic queues are separate from each other. Additionally, two service strategies, first-come-first-service (FCFS) and absolute service (ABS) are investigated. Finally, the performance of the proposed scheme is evaluated and compared with those of other priority schemes.[[fileno]]2030201030040[[department]]資訊工程學
Current standards reserve one bit in the ATM cell header to indicate loss priority. When congestion ...
Performance of ATM networks depends on switch performance and architecture. This paper presents a si...
Input buffered switches are known to suffer from head-of-line (HOL) blocking that limits the through...
[[abstract]]In this paper, cell loss priority schemes in the ATM switches are studied. Many schemes ...
We propose a Mixed Priority Queueing (MPQ) model to improve the Quality Of Service (QOS) for 3 diffe...
Buffer management and cell scheduling are the most important factors affecting the design of packet...
[[abstract]]This paper concerns with the problem of supporting multiple QoS classes for BISDN servic...
In this paper, we propose an N × N high speed and non-blocking asynchronous transfer mode (ATM) swit...
[[abstract]]Sharing buffer space between switch ports greatly improves the performance of the switch...
AbstractIn this paper, we propose a versatile scheduling discipline, called Precedence with Partial ...
The impact of buffer management and priority scheduling is examined in stressful scenarios when the ...
Abst ract-- In this paper, we propose a versatile scheduling discipline, called Precedence with Part...
Abstract. The main concerns in designing the multistage switching fabrics are speed, throughput, del...
A number of recent studies have addressed the use of priority mechanisms in Asynchronous Transfer Mo...
A highly efficient asynchronous transfer mode (ATM) switches using crossbar type structure is propos...
Current standards reserve one bit in the ATM cell header to indicate loss priority. When congestion ...
Performance of ATM networks depends on switch performance and architecture. This paper presents a si...
Input buffered switches are known to suffer from head-of-line (HOL) blocking that limits the through...
[[abstract]]In this paper, cell loss priority schemes in the ATM switches are studied. Many schemes ...
We propose a Mixed Priority Queueing (MPQ) model to improve the Quality Of Service (QOS) for 3 diffe...
Buffer management and cell scheduling are the most important factors affecting the design of packet...
[[abstract]]This paper concerns with the problem of supporting multiple QoS classes for BISDN servic...
In this paper, we propose an N × N high speed and non-blocking asynchronous transfer mode (ATM) swit...
[[abstract]]Sharing buffer space between switch ports greatly improves the performance of the switch...
AbstractIn this paper, we propose a versatile scheduling discipline, called Precedence with Partial ...
The impact of buffer management and priority scheduling is examined in stressful scenarios when the ...
Abst ract-- In this paper, we propose a versatile scheduling discipline, called Precedence with Part...
Abstract. The main concerns in designing the multistage switching fabrics are speed, throughput, del...
A number of recent studies have addressed the use of priority mechanisms in Asynchronous Transfer Mo...
A highly efficient asynchronous transfer mode (ATM) switches using crossbar type structure is propos...
Current standards reserve one bit in the ATM cell header to indicate loss priority. When congestion ...
Performance of ATM networks depends on switch performance and architecture. This paper presents a si...
Input buffered switches are known to suffer from head-of-line (HOL) blocking that limits the through...