Design of the integrated parallel processing unit IPU with systolic VLSI chips

[[abstract]]The design of a massively parallel processing system IPU (integrated parallel processing unit) is described. It is a two-dimensional mesh-connected parallel processing array operated in SIMD (single instruction, multiple data) fashion and attached to a host computer. The IPU array is implemented with 64 systolic VLSI (very-large-scale integration) chips each of which consists of four processing elements. A hardware interface that acts as a bridge between host computer and the IPU array has also been designed. A high-level programming language environment for designing the parallel program to run on this array is provided. Several applications are discussed. Some experimental results on the execution speed of the IPU system are reported.[[fileno]]2030201030015[[department]]資訊工程學