Technology mapping and circuit depth optimization for field programmable gate arrays

[[abstract]]Programmable Gate Arrays (PGAs) are important media for rapid system prototyping. In this paper, we propose a two step technology mapping algorithm for lookup table type FPGAs. In the first step, the technology mapper attempts to minimize the total number of TLUs used and at the same time to keep the length of the critical path short. Then, it is followed by a rule based postprocessor which maximally decreases the depth of a circuit.[[fileno]]2030219030025[[department]]資訊工程學