Design a simple and high performance switch using a two-stage architecture

[[abstract]]Recently, there is tremendous interest in the research of two-stage switches. Unlike input-buffered switches, two-stage switches do not need to find matchings between inputs and outputs. However, two-stage switches usually suffer from the out-of-sequence problem. To design a simple and high performance switch using the two-stage architecture, we address three buffer design problems in this paper: re-sequencing buffers, central buffers and input buffers. We show that the size of the resequencing buffer needs to be proportional to the size of the central buffer to ensure that no packets are lost due to resequencing. Via simulations, we find that a moderate size of central buffer yields good throughput when traffic is not bursty. However, when the traffic is bursty, one needs to address the head-of-line blocking problem at the input. We also find that using the round-robin service policy for multiple virtual output queues at inputs may exhibit a catastrophic phenomenon, called a non-ergodic mode. When a switch is trapped in a non-ergodic mode, its throughput is sharply reduced. To solve such a problem in input buffers, we show that one may introduce "randomness" into a switch to jump out of a non-ergodic mode.[[fileno]]2030221030010[[department]]資訊工程學