[[abstract]]Given the geometry of wires for interconnections, the authors want to assign two conducting layers to the segments of these wires so that the number of vias required is minimized. This layer assignment problem, also referred to as the via minimization problem, has been formulated as finding a maximum cut of a planar graph. The authors propose a novel algorithm for optimal layer assignment under a general model where the planar graph has real-valued edge weights. The time complexity of the proposed algorithm is O(n3/2 log n) where n is the number of wire-segment clusters in a given layout. In contrast, all existing optimal algorithms for layer assignment have the time complexity of O(n3).[[fileno]]2030218030007[[department]]資訊工程學
We consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring problem is ...
Layer assignment is an important post-layout optimization technique in very large scale integrated c...
AbstractWe consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring pro...
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit ...
As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit...
As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of cir...
In the design of integrated circuits (ICs), it is important to minimize the number of vias between c...
[[abstract]]We propose a new layer assignment approach for the k-layer Constrained Via Minimization ...
The design of very large scale integrated (VLSI) chips is an exciting area of applied discrete mathe...
This paper presents an efficient and practical approach to the Constrained Via Minimization (CVM) pr...
Vias between different layers of interconnection on dense integrated circuits tend to reduce yield, ...
AbstractThis paper outlines an algorithm for optimum linear ordering (OLO) of a weighted parallel gr...
[[abstract]]The previous constrained via minimization problem for VLSI previous three-layer routing...
Several applications use algorithms for drawing k-layered networks and, in particular, 2-layered net...
[[abstract]]Antenna effect is an important issue that needs to be considered in the routing stage fo...
We consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring problem is ...
Layer assignment is an important post-layout optimization technique in very large scale integrated c...
AbstractWe consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring pro...
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit ...
As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit...
As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of cir...
In the design of integrated circuits (ICs), it is important to minimize the number of vias between c...
[[abstract]]We propose a new layer assignment approach for the k-layer Constrained Via Minimization ...
The design of very large scale integrated (VLSI) chips is an exciting area of applied discrete mathe...
This paper presents an efficient and practical approach to the Constrained Via Minimization (CVM) pr...
Vias between different layers of interconnection on dense integrated circuits tend to reduce yield, ...
AbstractThis paper outlines an algorithm for optimum linear ordering (OLO) of a weighted parallel gr...
[[abstract]]The previous constrained via minimization problem for VLSI previous three-layer routing...
Several applications use algorithms for drawing k-layered networks and, in particular, 2-layered net...
[[abstract]]Antenna effect is an important issue that needs to be considered in the routing stage fo...
We consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring problem is ...
Layer assignment is an important post-layout optimization technique in very large scale integrated c...
AbstractWe consider the wiring or layer assignment problem for edge-disjoint layouts. The wiring pro...