[[abstract]]We summarize the experience of estimating the average power dissipation of a security processor (of 430K gates) using an in-house tool, called ToggleFinder. The estimation is done at the register-transfer level (RTL) so that the CPU time can be slashed dramatically. At the same time, the accuracy is retained by two techniques: power mode classification and scalable linear approximation. We found that a security processor containing a number of different encryption and decryption schemes, such as AES and RSA, could consume power very differently from one clock cycle to another. Also, the design gate count of a design block does not reflect how much power it consumes very well. Such a large design demonstrates that our new power e...
This manual describes how to use PowerChecker version 4.1, the CAD tool for the estimation and opti...
In the last three decades we have witnessed a remarkable development in the area of integrated circu...
This paper proposes a novel system-level power estima-tion methodology for electronic designs consis...
[[abstract]]Power estimation at the register transfer level (RTL) often suffers from inadequate accu...
[[abstract]]In this paper, we present the power estimation methodologies for the development of a lo...
[[abstract]]We propose a hybrid power model for estimating the power dissipation of a design at the ...
The increased complexity and low-power requirements of integrated circuit design demands reliable an...
We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. Th...
Conference of 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conf...
We present techniques for estimating switching activity and power consumption in register-transfer l...
We will present a power estimation technique for digital integrated circuits that operates at the re...
New and complex systems are being implemented using highly advanced Electronic Design Automation (ED...
The recent growing demand for portable computing and personal communication applications combined wi...
High level synthesis is the process of generating register transfer (RT) level designs from behavior...
textThe widespread use of microprocessor chips in high performance applications like graphics simul...
This manual describes how to use PowerChecker version 4.1, the CAD tool for the estimation and opti...
In the last three decades we have witnessed a remarkable development in the area of integrated circu...
This paper proposes a novel system-level power estima-tion methodology for electronic designs consis...
[[abstract]]Power estimation at the register transfer level (RTL) often suffers from inadequate accu...
[[abstract]]In this paper, we present the power estimation methodologies for the development of a lo...
[[abstract]]We propose a hybrid power model for estimating the power dissipation of a design at the ...
The increased complexity and low-power requirements of integrated circuit design demands reliable an...
We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. Th...
Conference of 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 ; Conf...
We present techniques for estimating switching activity and power consumption in register-transfer l...
We will present a power estimation technique for digital integrated circuits that operates at the re...
New and complex systems are being implemented using highly advanced Electronic Design Automation (ED...
The recent growing demand for portable computing and personal communication applications combined wi...
High level synthesis is the process of generating register transfer (RT) level designs from behavior...
textThe widespread use of microprocessor chips in high performance applications like graphics simul...
This manual describes how to use PowerChecker version 4.1, the CAD tool for the estimation and opti...
In the last three decades we have witnessed a remarkable development in the area of integrated circu...
This paper proposes a novel system-level power estima-tion methodology for electronic designs consis...