[[abstract]]Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we proposed a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the above linear constraints with a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. In the diagnosis framework, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category...
[[abstract]]We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-ev...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
Abstract The implementation of a system for analyzing circuits with respect to their path-delay faul...
[[abstract]]Diagnosis tools can be used to speed up the process for finding the root causes of funct...
[[abstract]]In this paper, we apply a technique to improve diagnosis resolution for delay faults. Th...
[[abstract]]Traditionally, diagnosis methods use static models for delay defects, while there exists...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
[[abstract]]Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we e...
[[abstract]]In this paper, we propose a new methodology for diagnosis of delay defects in the deep s...
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diag...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
[[abstract]]We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-ev...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
Abstract The implementation of a system for analyzing circuits with respect to their path-delay faul...
[[abstract]]Diagnosis tools can be used to speed up the process for finding the root causes of funct...
[[abstract]]In this paper, we apply a technique to improve diagnosis resolution for delay faults. Th...
[[abstract]]Traditionally, diagnosis methods use static models for delay defects, while there exists...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
The failure of devices due to timing-related defects is becoming increasingly prominent in the nanom...
[[abstract]]Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we e...
[[abstract]]In this paper, we propose a new methodology for diagnosis of delay defects in the deep s...
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diag...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
[[abstract]]We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-ev...
[[abstract]]A novel fault model for detecting delay defects of FPGAs is proposed in this paper. Our ...
Abstract The implementation of a system for analyzing circuits with respect to their path-delay faul...