[[abstract]]Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packard's HTVE (HP Interconnect Value Extractor)[[fileno]]2030232010002[[department]]資訊工程學
Today's data-dominated and high-performance applications require the integration of over 1 billion t...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow...
The goals of the work presented in this paper were to estimate quantitatively the impact of intercon...
Abstrnct-The propagation delay of interconnection lines is a major factor in determining the perform...
117 p.Increased use of technology in day to day life for seamless activity and increased living comf...
ABSTRACT In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct fun...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
This research focuses on the future of integrated circuit (IC) scaling technologies at the device an...
This book covers layout design and layout migration methodologies for optimizing multi-net wire stru...
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance ef...
Interconnect has become the dominating factor in determining circuit performance and reliability in ...
With the rapid developments in VLSI technology, design, and CAD techniques, at both the chip and pac...
The Information Revolution and enabling era of silicon ul-tralarge-scale integration (ULSI) have spa...
Today's data-dominated and high-performance applications require the integration of over 1 billion t...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow...
The goals of the work presented in this paper were to estimate quantitatively the impact of intercon...
Abstrnct-The propagation delay of interconnection lines is a major factor in determining the perform...
117 p.Increased use of technology in day to day life for seamless activity and increased living comf...
ABSTRACT In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct fun...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
This research focuses on the future of integrated circuit (IC) scaling technologies at the device an...
This book covers layout design and layout migration methodologies for optimizing multi-net wire stru...
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance ef...
Interconnect has become the dominating factor in determining circuit performance and reliability in ...
With the rapid developments in VLSI technology, design, and CAD techniques, at both the chip and pac...
The Information Revolution and enabling era of silicon ul-tralarge-scale integration (ULSI) have spa...
Today's data-dominated and high-performance applications require the integration of over 1 billion t...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow...