Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams

[[abstract]]This paper proposes an efficient algorithm for technology mapping targeting table look-up (TLU) blocks. It is capable of minimizing either the number of TLU's used or the depth of the produced circuit. Our approach consists of two steps. First a network of super nodes, is created. Next a Boolean function of each super node with an appropriate don't care set is decomposed into a network of TLU's. To minimize the circuit's depth, several rules are applied on the critical portion of the mapped circuit.[[fileno]]2030202010011[[department]]資訊工程學