[[abstract]]An AND-type split-gate Flash memory cell with a trench select gate and a buried n+ source is proposed. This cell, programmed by ballistic source side injection (BSSI), can provide high programming efficiency with a cell size of 5F(2). Furthermore, both the programming speed and the read current are enhanced by the shared select gate configuration.[[fileno]]2030158010011[[department]]電機工程學
We present a novel non-volatile memory cell architecture, which remarkably impro...
The aim of this paper is to give a thorough overview of Flash memory cells. Basic operations and cha...
Scaling down of conventional flash memory technology faces difficult technical challenges and some p...
[[abstract]]© 2006 Japanese Journal of Applied Physics-In this paper, a novel ballistic-injection AN...
[[abstract]]This work proposes a novel p-type boron-doped floating gate for n-channel split-gate fla...
A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D ...
[[abstract]]In this paper, we present an analytical solution for evaluating the ramped-pulse program...
The flash memory technology meets physical and technical obstacles in further scaling. New structure...
With the growth of the multi-media applications in portable electronic products, the demand of ultra...
[[abstract]]© 2005 Japanese Journal of Applied Physics-A novel flash memory cell fabricated by stand...
[[abstract]]This work numerically elucidates the considerations and optimizations of nanoscale Schot...
[[abstract]]This paper presents a compact and accurate analytical model for evaluating the programmi...
In this paper, a Flash memory structure with the floating-gate at the opposite side of conduction ch...
[[abstract]]This work numerically elucidates the considerations and optimizations of nanoscale Schot...
[[abstract]]We propose a new Body-Effect-assisted NOR-type (BeNOR) flash memory for multilevel stora...
We present a novel non-volatile memory cell architecture, which remarkably impro...
The aim of this paper is to give a thorough overview of Flash memory cells. Basic operations and cha...
Scaling down of conventional flash memory technology faces difficult technical challenges and some p...
[[abstract]]© 2006 Japanese Journal of Applied Physics-In this paper, a novel ballistic-injection AN...
[[abstract]]This work proposes a novel p-type boron-doped floating gate for n-channel split-gate fla...
A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D ...
[[abstract]]In this paper, we present an analytical solution for evaluating the ramped-pulse program...
The flash memory technology meets physical and technical obstacles in further scaling. New structure...
With the growth of the multi-media applications in portable electronic products, the demand of ultra...
[[abstract]]© 2005 Japanese Journal of Applied Physics-A novel flash memory cell fabricated by stand...
[[abstract]]This work numerically elucidates the considerations and optimizations of nanoscale Schot...
[[abstract]]This paper presents a compact and accurate analytical model for evaluating the programmi...
In this paper, a Flash memory structure with the floating-gate at the opposite side of conduction ch...
[[abstract]]This work numerically elucidates the considerations and optimizations of nanoscale Schot...
[[abstract]]We propose a new Body-Effect-assisted NOR-type (BeNOR) flash memory for multilevel stora...
We present a novel non-volatile memory cell architecture, which remarkably impro...
The aim of this paper is to give a thorough overview of Flash memory cells. Basic operations and cha...
Scaling down of conventional flash memory technology faces difficult technical challenges and some p...