[[abstract]]Presents a complete fault-tolerant programmable logic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and multiple stuck-at, bridging, and crosspoint faults. The results of this study show that the total augmented area overhead for both repair and fault diagnosis is nearly 15 to 25 percent over the original PLA, but the chip yield can be improved significantly[[fileno]]2030110010010[[department]]電機工程學
none5Several alternative building blocks have been proposed to replace planar transistors, among whi...
The problem of determining a minimal number of control inputs for converting a programmable logic ar...
Abstract. Functional testing, as opposed to parametric testing, plays an important role in testing V...
[[abstract]]The yield of ICs has always been crucial to the commercial success of their manufacture....
[[abstract]]A defect-tolerant PLA (programmable logic array) design with a simple column folding tec...
AbstractIn this paper we propose a new technique for designing easily testable PLAs. Our design is a...
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The...
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). Th...
In this paper, the validity of'single fault assumption in deriving diagnostic test sets is examined...
An on-line algorithm is developed for the location of\ud single cross point faults in a PLA (FPLA). ...
145 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1982.This research has mainly cent...
Abstract: We present a method for obtaining a minimal set of test configurations and their associate...
[[abstract]]A new design to reduce the overhead required for a fully testable PLA is proposed. This ...
An improved method which generates tests for multiple crosspoint faults in PLAs has been realized th...
Abstract — The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectro...
none5Several alternative building blocks have been proposed to replace planar transistors, among whi...
The problem of determining a minimal number of control inputs for converting a programmable logic ar...
Abstract. Functional testing, as opposed to parametric testing, plays an important role in testing V...
[[abstract]]The yield of ICs has always been crucial to the commercial success of their manufacture....
[[abstract]]A defect-tolerant PLA (programmable logic array) design with a simple column folding tec...
AbstractIn this paper we propose a new technique for designing easily testable PLAs. Our design is a...
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The...
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). Th...
In this paper, the validity of'single fault assumption in deriving diagnostic test sets is examined...
An on-line algorithm is developed for the location of\ud single cross point faults in a PLA (FPLA). ...
145 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1982.This research has mainly cent...
Abstract: We present a method for obtaining a minimal set of test configurations and their associate...
[[abstract]]A new design to reduce the overhead required for a fully testable PLA is proposed. This ...
An improved method which generates tests for multiple crosspoint faults in PLAs has been realized th...
Abstract — The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectro...
none5Several alternative building blocks have been proposed to replace planar transistors, among whi...
The problem of determining a minimal number of control inputs for converting a programmable logic ar...
Abstract. Functional testing, as opposed to parametric testing, plays an important role in testing V...