Tuning stationary iterative solvers for fault resilience

Actes del 6th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA '15)As the transistor’s feature size decreases following Moore’s Law, hardware will become more prone to permanent, intermittent, and transient errors, increasing the number of failures experienced by applications, and diminishing the confidence of users. As a result, resilience is considered the most difficult under addressed issue faced by the High Performance Computing community. In this paper, we address the design of error resilient iterative solvers for sparse linear systems. Contrary to most previous ap- proaches, based on Krylov subspace methods, for this purpose we analyze stationary component-wise relaxation. Concretely, starting from a plain implementation of the Jacobi iteration, we design a low-cost component-wise technique that elegantly handles bit-flips, turning the initial synchronized solver into an asynchronous itera- tion. Our experimental study employs sparse incomplete factoriza- tions from several practical applications to expose the convergence delay incurred by the fault-tolerant implementation.his work was partly funded by the U.S. Department of Energy (Award Number DE-SC-0010042), and the Russian Scientific Foun- dation (Agreement N14-11-00190). E. S. Quintana-Ortí was sup- ported by projects TIN2011-23283 and TIN2014-53495-R of the Spanish Ministerio de Economía y Competitividad