A power aware partitioning framework for hardware-software codesign

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references (leaves 34-37).Issued also on microfiche from Lange Micrographics.Existing approaches in hardware-software partitioning do not consider the maximum available system power while making the partitioning decision. Such a decision is sensitive to design efficiency when the target system is reconfigurable and supports multiple applications. Since partitioning and scheduling are interdependent, neglecting the available system power could result in an infeasible schedule. In this thesis, we present a power-aware partitioning technique for embedded systems that could support a set of applications. The applications specified at a task level of granularity are partitioned and scheduled such that timing and maximum available system power constraints are satisfied with minimum hardware logic