High level power estimation of cache and TLB using complete machine simulation

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references (leaves 37-40).Issued also on microfiche from Lange Micrographics.The power dissipation of the modern processor has rapidly increased along with increasing transistor counts and clock frequencies. This is detrimental to the battery lifetime in the embedded processor, and also to the reliability. Therefore, designing a processor with the intent of minimizing system costs, especially that arise from high power consumption, requires attention at all design stages. Thus, power estimation tools are required in all the design stages and tools exist to perform power-estimation and optimization a lower levels of abstraction. While these tools typically provide accurate results, it is often difficult to use the estimates to make optimization at the higher levels. These tools are reasonably mature; however greater attention is necessary at higher abstraction levels. As power becomes a critical design constraint, there is a need to open the power problems to the architects and compiler writers also, thus leading to a design, which is optimized for power and performance. The goal of this thesis is to address the power problem in embedded processors and propose a methodology for high-level power estimation and optimization. The primary objective of high-level power estimation is the ability to quickly decide which solution utilizes minimal power rather than determining the accurate amount of power dissipation. Upon the best solution determination, a more accurate estimate may be given at the lower levels of abstraction. After system design, the power optimization can be performed at any design stage. Among all techniques, the optimization problems can be formulated more precisely at the circuit level. Significant improvements are possible in cell based designs such as memories. There are important techniques such as voltage cell reduction and memory cell redesign. Our methodology is based on the memory cell redesign, specifically the redesign of the content addressable memory (CAM). In this work, we estimate the power dissipation in the cache and the Translation Lookaside Buffer (TLB) of an embedded processor. In order to get an accurate estimate, we combine the power models derived from the transistor level structures with a complete machine simulator