Design and analysis of a fault tolerant network processor

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references: p. 51-53.Issued also on microfiche from Lange Micrographics.This thesis investigates the effect of transient faults on a processor and proposes on-chip fault tolerant design techniques to improve its reliability. The target processor is a general 32-bit, four stage pipeline, dual context RISC style design used at network interface. Fault injection simulation using single bitflip in the gate-level description of the processor is used to determine software-level impact of the transient faults in the processor. The design emphasis is on maximizing reliability of the processor under application software which typically runs in a network environment. The cost benefits of fault tolerant design are quantified using fault injection simulation