Increasing power density with technology scaling has caused stagnation in operating frequency of modern day microprocessors. This has led designers to prefer multicore architectures over complex monolithic processors to keep up with the demand for rising computing throughput. Although processing units are getting smaller and simpler, the dramatic rise of their count on a single die has made the fabric that connects these processing units increasingly complex. These interconnect fabrics have become a bottleneck in improving overall system effciency. As a result, the design paradigm for multi-core chips is gradually shifting from a core-centric architecture towards an interconnect-centric architecture, where system efficiency is limited by th...
Journal ArticleIt is expected that future on-chip networks for many-core processors will impose hug...
High-performance routers have the task of transmitting traffic in be-tween the nodes of the Internet...
In the past those looking to accelerate computationally intensive applications through hardware impl...
A scalable architecture to design high radix switch fabric is presented. It uses circuit techniques ...
The ever-increasing demand for performance scaling has made multi-core (2-8 cores) chips prevalent i...
Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire dela...
Abstract—This work revisits the design of crossbar and high-radix interconnects in light of advances...
Recent advances in technology have made it possible to integrate systems with CPUs, memory units, bu...
Inter- and intra-chip connections have become the new challenge to enable the scaling of computing s...
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and...
With advances in technology, future multicore systems scaled to 100s and 1000s of cores/accelerators...
University of Minnesota Ph.D. dissertation. August 2012. Major: Electrical Engineering. Advisor: Sac...
The switching capacity of an Internet router is often dictated by the memory bandwidth required to b...
Journal ArticleThe paper presents a preliminary evaluation of novel techniques that address a growi...
This thesis describes a class of interconnection networks based on the use of a switch matrix to pro...
Journal ArticleIt is expected that future on-chip networks for many-core processors will impose hug...
High-performance routers have the task of transmitting traffic in be-tween the nodes of the Internet...
In the past those looking to accelerate computationally intensive applications through hardware impl...
A scalable architecture to design high radix switch fabric is presented. It uses circuit techniques ...
The ever-increasing demand for performance scaling has made multi-core (2-8 cores) chips prevalent i...
Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire dela...
Abstract—This work revisits the design of crossbar and high-radix interconnects in light of advances...
Recent advances in technology have made it possible to integrate systems with CPUs, memory units, bu...
Inter- and intra-chip connections have become the new challenge to enable the scaling of computing s...
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and...
With advances in technology, future multicore systems scaled to 100s and 1000s of cores/accelerators...
University of Minnesota Ph.D. dissertation. August 2012. Major: Electrical Engineering. Advisor: Sac...
The switching capacity of an Internet router is often dictated by the memory bandwidth required to b...
Journal ArticleThe paper presents a preliminary evaluation of novel techniques that address a growi...
This thesis describes a class of interconnection networks based on the use of a switch matrix to pro...
Journal ArticleIt is expected that future on-chip networks for many-core processors will impose hug...
High-performance routers have the task of transmitting traffic in be-tween the nodes of the Internet...
In the past those looking to accelerate computationally intensive applications through hardware impl...