Modeling Floating Body Memory Devices

TCAD simulations have been performed using SILVACO ATLAS 2D device simulator for a Zero-Capacitor Random Access Memory, a new generation memory cell which is being researched as an alternative for DRAM memory cells in order to get rid of the bulky storage capacitor. In our study we have taken into consideration, a Dual Gate - ZRAM (DGZRAM) as it helps reduce drain-induced barrier lowering and hence leakage, while having better control of the charge in the substrate, The states are written into the device using impact ionization to generate a large number of holes in the substrate, which alter the threshold voltage of the device. The effect of the gate oxide thickness and substrate body thickness are being taken into consideration to increase the change in the threshold voltage and thereby the noise margin. A DGZRAM structure with a Quantum Well introduced into the substrate via a SiGe layer was also simulated. The quantum well introduces a hole storage pocket in the substrate. Comparisons in terms of noise margin, have been made for both the devices which show that the structure with the quantum well in the substrate performs better than the bulk structure. The effect of impact ionization on the electron and hole concentrations have been shown for both the devices. Simulations have been performed taking into consideration gate electrodes with different work functions and it has been observed that while n-polysilicon has a detrimental impact in MOSFETs due to high off-state leakage current, it can be used to obtain low power memory cells. Parameters such as the quantum well doping, composition of Ge in the quantum well, channel length of the device, SiGe layer thickness and its position with respect to the top gate have been varied to obtain the optimum noise margin for the device