A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs

This paper proposes a novel approach to reducing the size of FPGA reconfiguration bits reams by fixing appropriate orders for LUT inputs. With such LUT input orders, memory locations that need to be altered during partial reconfiguration are relocated into common frames. We present a novel problem formulation that relates the number of frames (that need to be downloaded into FPGAs) to the number of minterms of a specially constructed logic function. A heuristic procedure is developed to solve the formulated problem in polynomial time. The proposed methodology is validated by experiments conducted on Xilinx Virtex FPGA platform. Considerable reduction on the size of reconfiguration bitstreams have been observed from our experimental results