Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks required for spectral shaping and for an M-channel channelizer. In an under-decimated (non-maximally decimated) polyphase filter bank scenario, where the number of data-loads is less than the number of sub-filters, the serial polyphase structure with parallel MAC approach requires a larger processing time than the corresponding data-load time. In order to meet the output time constraint, the serial polyphase structure with parallel MAC has to run at a higher clock rate than the data input rate and hence potentially consumes high power. In contrast to the Load-Process Architecture (LPA), a Run-time Architecture (RA) operating only at twice the input data rate is presented which efficiently schedules the sub-filter's processing within the data-load time. The RA offers time and power efficient structure for the presented up- and down-sample polyphase filters utilizing 9% and 11% slice LUTs and 10% and 13% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively