Ranking process parameter association with low yield wafers using spec-out event network analysis

In the semiconductor process, the time-series process sensor data such as temperature, pressure, and voltage, are analyzed, to find suspicious process parameters associated with low yield wafers. A common approach is to compute correlation between individual spec-out events and defect ratios. However, the downside with this approach is that it ignores interactions among spec-out events, leading to each spec-out event being independently administrated. In this paper, we propose a novel approach that incorporates the interactions among spec-out events using spec-out event network analysis. We construct a weighted directed graph in which a spec out event is represented as a node, a precedence relation between events as a directed edge, and the wafer defect ratio corresponding to the relation as an edge weight. In this graph, a more important node in the process will have more links from other succeeding nodes with high defect ratios. The PageRank algorithm run on this event network results in a ranking of association with wafer defects. We validated the performance using real-production data from a 32 nm device. The proposed method enables process engineers to determine the root causes of low yield wafers due to the interactions of the process steps.OAIID:RECH_ACHV_DSTSH_NO:T201734252RECH_ACHV_FG:RR00200001ADJUST_YN:EMP_ID:A004522CITE_RATE:3.195DEPT_NM:산업공학과EMAIL:zoon@snu.ac.krSCOPUS_YN:YN