Design and Implementation of a New Framework for Post-Synthesis Obfuscation with a Mixture of Multiple Cells with an Integrated Anti-SAT Block

This paper proposes a new framework for post-synthesis obfuscation of digital circuits using a mixture of cells combined with an Anti-SAT block. Furthermore, a novel integrated framework has been established wherein obfuscation, along with Anti-SAT and validation of the benchmarks, progress through MATLAB®, Python, Cadence RTL Encounter® and Cadence LEC® to implement the proposed methodology. Area, delay, leakage power and total power are adopted as elements of the evaluation matrix. These parameters are compared between the original circuit, the circuit after obfuscation, the circuit after integration with Anti-SAT and the circuit after implementation of the proposed method of multiple-cell obfuscation with Anti-SAT. The probability of breaking a circuit is taken as the security criterion. It is mathematically proven that as the number of types of obfuscated cells used increases, then the probability of breaking the circuit decreases. The results obtained accord with the mathematical proof. The framework minimizes the delay by inserting obfuscation cells (OCs) in the non-critical paths, strengthens the security by using several types of OCs and allows the user to select a design based on justified area, leakage power and total power. However, against a Boolean SATisfiability (SAT) attack, obfuscation with multiple cells is not a sufficient defense. An Anti-SAT block performs better than obfuscation but has its own limitations. Thus, use of an Anti-SAT block in combination with multiple-cell obfuscation is proposed and implemented, giving better results against an efficient SAT attack. The number of iterations, as well as runtime to obtain the correct keys, increase significantly for the Anti-SAT block combined with multiple-cell obfuscation compared to the Anti-SAT or obfuscation block alone