Pendse, R.; Kushanagar, N.; Walterscheidt, U.; , "Investigation of impact of victim cache and victim tracer on a fully associative disk cache," Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on, vol., no., pp.78-81, 9-12 Aug 1998.doi: 10.1109/MWSCAS.1998.759439In this paper, we present results of investigation to study the impact of victim cache and victim tracer on the miss rates due to the LRU block replacement algorithm. A total of three different algorithms were implemented. They include the basic LRU, LRU with victim cache, and LRU with victim tracer. All the algorithms were implemented as a part of a disk cache. For victim cache and victim tracer, a unique priority scheme was used. Extensive simulations were performed...
A new buffer replacement scheme, called DEAR (DEtection-based Adaptive Replacement), is presented fo...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Because of the infeasibility or expense of large fully-associative caches, cache memories are often ...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
As processors become faster, memory performance becomes a serious bottleneck. In recent years memor...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
This thesis describes a model used to analyze the replacement decisions made by LRU and OPT (Least-R...
As processors become faster, memory hierarchy becomes a serious bottleneck. In recent years memory ...
Caches mitigate the long memory latency that limits the performance of modern processors. However, c...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Memory latency has become an important performance bottleneck in current microprocessors. This probl...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Block replacement refers to the process of selecting a block of data or a cache line to be evicted o...
Classic cache replacement policies assume that miss costs are uniform. However, the correlation betw...
A new buffer replacement scheme, called DEAR (DEtection-based Adaptive Replacement), is presented fo...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Because of the infeasibility or expense of large fully-associative caches, cache memories are often ...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
As processors become faster, memory performance becomes a serious bottleneck. In recent years memor...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
This thesis describes a model used to analyze the replacement decisions made by LRU and OPT (Least-R...
As processors become faster, memory hierarchy becomes a serious bottleneck. In recent years memory ...
Caches mitigate the long memory latency that limits the performance of modern processors. However, c...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Memory latency has become an important performance bottleneck in current microprocessors. This probl...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Block replacement refers to the process of selecting a block of data or a cache line to be evicted o...
Classic cache replacement policies assume that miss costs are uniform. However, the correlation betw...
A new buffer replacement scheme, called DEAR (DEtection-based Adaptive Replacement), is presented fo...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Because of the infeasibility or expense of large fully-associative caches, cache memories are often ...